thank you.Other than having one of aBUGSworstnightmare's dev boards, I have no significant information or experience for these TI chips.
4 lane DSI can have one foible that being 3 bytes per pixel, splitting across 4 lanes means that unless the width is a multiple of 3 the amount of data sent on each lane can vary as it splits at a byte level between the lanes. That shouldn't be an issue with 1920 though.
Due to the integer divide on the DSI PLL, you will generally need to use an external clock on these devices. Trying to lock off the DSI clock when it's not at the pixel rate will cause issues.
we don't have external clock on board,
so abandoned 4-lane attempt, still use 3-lane.
just have to debug the flicker issue.
thank you for your kindly reply.
Statistics: Posted by dcrane — Tue Apr 29, 2025 1:47 am